Semiconductor Device and Method of Forming 3D Inductor from Prefabricated Pillar Frame

ABSTRACT

A semiconductor device is made by mounting a semiconductor component over a carrier. A ferromagnetic inductor core is formed over the carrier. A pillar frame including a plurality of bodies is mounted over the carrier, semiconductor component, and inductor core. An encapsulant is deposited around the semiconductor component, plurality of bodies, and inductor core. A portion of the pillar frame is removed. A first remaining portion of the pillar frame bodies provide inductor pillars around the inductor core and a second remaining portion of the pillar frame bodies provide an interconnect pillar. A first interconnect structure is formed over a first surface of the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected to the inductor pillars to form one or more 3D inductors.

CLAIM OF DOMESTIC PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 12/467,908, filed May 18, 2009, and claims priority to theforegoing parent application pursuant to 35 U.S.C. §120.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device and method of forming a 3Dinductor from a prefabricated pillar frame.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Discrete semiconductor devices generally contain one type ofelectrical component, e.g., light emitting diode (LED), small signaltransistor, resistor, capacitor, inductor, and power metal oxidesemiconductor field effect transistor (MOSFET). Integrated semiconductordevices typically contain hundreds to millions of electrical components.Examples of integrated semiconductor devices include microcontrollers,microprocessors, charged-coupled devices (CCDs), solar cells, anddigital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such ashigh-speed calculations, transmitting and receiving electromagneticsignals, controlling electronic devices, transforming sunlight toelectricity, and creating visual projections for television displays.Semiconductor devices are found in the fields of entertainment,communications, power conversion, networks, computers, and consumerproducts. Semiconductor devices are also found in military applications,aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductormaterials. The atomic structure of semiconductor material allows itselectrical conductivity to be manipulated by the application of anelectric field or through the process of doping. Doping introducesimpurities into the semiconductor material to manipulate and control theconductivity of the semiconductor device.

A semiconductor device contains active and passive electricalstructures. Active structures, including bipolar and field effecttransistors, control the flow of electrical current. By varying levelsof doping and application of an electric field or base current, thetransistor either promotes or restricts the flow of electrical current.Passive structures, including resistors, capacitors, and inductors,create a relationship between voltage and current necessary to perform avariety of electrical functions. The passive and active structures areelectrically connected to form circuits, which enable the semiconductordevice to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complexmanufacturing processes, i.e., front-end manufacturing, and back-endmanufacturing, each involving potentially hundreds of steps. Front-endmanufacturing involves the formation of a plurality of die on thesurface of a semiconductor wafer. Each die is typically identical andcontains circuits formed by electrically connecting active and passivecomponents. Back-end manufacturing involves singulating individual diefrom the finished wafer and packaging the die to provide structuralsupport and environmental isolation.

One goal of semiconductor manufacturing is to produce smallersemiconductor devices. Smaller devices typically consume less power,have higher performance, and can be produced more efficiently. Inaddition, smaller semiconductor devices have a smaller footprint, whichis desirable for smaller end products. A smaller die size may beachieved by improvements in the front-end process resulting in die withsmaller, higher density active and passive components. Back-endprocesses may result in semiconductor device packages with a smallerfootprint by improvements in electrical interconnection and packagingmaterials.

Another goal of semiconductor manufacturing is to produce higherperformance semiconductor devices. Increases in device performance canbe accomplished by forming active components that are capable ofoperating at higher speeds. In high frequency applications, such asradio frequency (RF) wireless communications, integrated passive devices(IPDs) are often contained within the semiconductor device. Examples ofIPDs include resistors, capacitors, and inductors. A typical RF systemrequires multiple IPDs in one or more semiconductor packages to performthe necessary electrical functions.

An integrated three dimensional (3D) inductor can be made by formingthrough mold via (TMV) in the encapsulant around a ferromagnetic corematerial, as described in US Publication 20080135977. The TMVs areplated to form metal inductor pillars which are electrically connectedin a coiled arrangement around the ferromagnetic core. The lithographyand plating processes needed to form the inductor pillars are timeconsuming and costly.

SUMMARY OF THE INVENTION

A need exists for 3D inductors without using costly lithography andplating processes to form the inductor pillars. Accordingly, in oneembodiment, the present invention is a method of making a semiconductordevice comprising the steps of providing a carrier, mounting asemiconductor component over the carrier, forming an inductor core overthe carrier, and mounting a pillar frame over the carrier andsemiconductor component. The pillar frame includes a plurality of bodieswith a first portion of the bodies being disposed around the inductorcore. The method further includes the steps of depositing an encapsulantaround the semiconductor component, plurality of bodies, and inductorcore, removing a portion of the pillar frame while leaving the firstportion of the bodies to form inductor pillars, forming a firstinterconnect structure over a first surface of the encapsulant, removingthe carrier, and forming a second interconnect structure over a secondsurface of the encapsulant opposite the first interconnect structure.The first and second interconnect structures are electrically connectedto the inductor pillars to form a 3D inductor.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a carrier,mounting a semiconductor component over the carrier, mounting a pillarframe over the carrier and semiconductor component, depositing anencapsulant over the semiconductor component and pillar frame, andremoving a portion of the pillar frame. A first remaining portion of thepillar frame provides inductor pillars. The method further includes thesteps of forming a first interconnect structure over a first surface ofthe encapsulant, removing the carrier, and forming a second interconnectstructure over a second surface of the encapsulant opposite the firstinterconnect structure. The first and second interconnect structures areelectrically connected to the inductor pillars to form a 3D inductor.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a carrier,mounting a semiconductor component over the carrier, mounting a pillarframe over the carrier and semiconductor component, depositing anencapsulant over the semiconductor component and pillar frame, removinga portion of the pillar frame, and forming a first interconnectstructure over a first surface of the encapsulant. A first remainingportion of the pillar frame provides inductor pillars. The firstinterconnect structure is electrically connected to the inductor pillarsto form a 3D inductor.

In another embodiment, the present invention is a semiconductor devicecomprising a semiconductor component and inductor core disposed inproximity to the semiconductor component. A pillar frame is mounted overthe semiconductor component and inductor core. An encapsulant isdeposited over the semiconductor component, pillar frame, and inductorcore. A portion of the pillar frame is removed to form inductor pillarsaround the inductor core. A first interconnect structure is formed overa first surface of the encapsulant. A second interconnect structure isformed over a second surface of the encapsulant opposite the firstinterconnect structure. The first and second interconnect structures areelectrically connected to the inductor pillars to form one or more 3Dinductors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a PCB with different types of packages mounted to itssurface;

FIGS. 2 a-2 c illustrate further detail of the representativesemiconductor packages mounted to the PCB;

FIGS. 3 a-3 k illustrate a process of using a prefabricated pillar frameto form interconnect pillars and inductor pillars around an inductorcore;

FIG. 4 illustrates the semiconductor device with 3D inductors andwithout interconnect pillars;

FIG. 5 illustrates the semiconductor device having multiple 3Dinductors;

FIG. 6 illustrates stacked semiconductor die with 3D inductors andinterconnect pillars;

FIG. 7 illustrates side-by-side semiconductor die with 3D inductors andinterconnect pillars;

FIG. 8 illustrates the semiconductor device with 3D inductors and ashielding layer formed over the semiconductor die;

FIG. 9 illustrates the semiconductor device with 3D inductors andcapacitor and resistor formed in build-up interconnect structure; and

FIG. 10 illustrates the semiconductor device with 3D inductors anddiscrete semiconductor components formed over the build-up interconnectlayer.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors and diodes, have the abilityto control the flow of electrical current. Passive electricalcomponents, such as capacitors, inductors, resistors, and transformers,create a relationship between voltage and current necessary to performelectrical circuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devices,transforming the semiconductor material into an insulator, conductor, ordynamically changing the semiconductor material conductivity in responseto an electric field or base current. Transistors contain regions ofvarying types and degrees of doping arranged as necessary to enable thetransistor to promote or restrict the flow of electrical current uponthe application of the electric field or base current.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition may involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

The layers can be patterned using photolithography, which involves thedeposition of light sensitive material, e.g., photoresist, over thelayer to be patterned. A pattern is transferred from a photomask to thephotoresist using light. The portion of the photoresist patternsubjected to light is removed using a solvent, exposing portions of theunderlying layer to be patterned. The remainder of the photoresist isremoved, leaving behind a patterned layer. Alternatively, some types ofmaterials are patterned by directly depositing the material into theareas or voids formed by a previous deposition/etch process usingtechniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern canexaggerate the underlying pattern and create a non-uniformly flatsurface. A uniformly flat surface is required to produce smaller andmore densely packed active and passive components. Planarization can beused to remove material from the surface of the wafer and produce auniformly flat surface. Planarization involves polishing the surface ofthe wafer with a polishing pad. An abrasive material and corrosivechemical are added to the surface of the wafer during polishing. Thecombined mechanical action of the abrasive and corrosive action of thechemical removes any irregular topography, resulting in a uniformly flatsurface.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual die and then packaging the die for structuralsupport and environmental isolation. To singulate the die, the wafer isscored and broken along non-functional regions of the wafer called sawstreets or scribes. The wafer is singulated using a laser cutting toolor saw blade. After singulation, the individual die are mounted to apackage substrate that includes pins or contact pads for interconnectionwith other system components. Contact pads formed over the semiconductordie are then connected to contact pads within the package. Theelectrical connections can be made with solder bumps, stud bumps,conductive paste, or wirebonds. An encapsulant or other molding materialis deposited over the package to provide physical support and electricalisolation. The finished package is then inserted into an electricalsystem and the functionality of the semiconductor device is madeavailable to the other system components.

FIG. 1 illustrates electronic device 50 having a chip carrier substrateor PCB 52 with a plurality of semiconductor packages mounted on itssurface. Electronic device 50 may have one type of semiconductorpackage, or multiple types of semiconductor packages, depending on theapplication. The different types of semiconductor packages are shown inFIG. 1 for purposes of illustration.

Electronic device 50 may be a stand-alone system that uses thesemiconductor packages to perform one or more electrical functions.Alternatively, electronic device 50 may be a subcomponent of a largersystem. For example, electronic device 50 may be a graphics card,network interface card, or other signal processing card that can beinserted into a computer. The semiconductor package can includemicroprocessors, memories, application specific integrated circuits(ASICs), logic circuits, analog circuits, RF circuits, discrete devices,or other semiconductor die or electrical components.

In FIG. 1, PCB 52 provides a general substrate for structural supportand electrical interconnect of the semiconductor packages mounted on thePCB. Conductive signal traces 54 are formed over a surface or withinlayers of PCB 52 using evaporation, electrolytic plating, electrolessplating, screen printing, or other suitable metal deposition process.Signal traces 54 provide for electrical communication between each ofthe semiconductor packages, mounted components, and other externalsystem components. Traces 54 also provide power and ground connectionsto each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels.First level packaging is a technique for mechanically and electricallyattaching the semiconductor die to an intermediate carrier. Second levelpackaging involves mechanically and electrically attaching theintermediate carrier to the PCB. In other embodiments, a semiconductordevice may only have the first level packaging where the die ismechanically and electrically mounted directly to the PCB.

For the purpose of illustration, several types of first level packaging,including wire bond package 56 and flip chip 58, are shown on PCB 52.Additionally, several types of second level packaging, including ballgrid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package(DIP) 64, land grid array (LGA) 66, multi-chip module (MCM) 68, quadflat non-leaded package (QFN) 70, and quad flat package 72, are shownmounted on PCB 52. Depending upon the system requirements, anycombination of semiconductor packages, configured with any combinationof first and second level packaging styles, as well as other electroniccomponents, can be connected to PCB 52. In some embodiments, electronicdevice 50 includes a single attached semiconductor package, while otherembodiments call for multiple interconnected packages. By combining oneor more semiconductor packages over a single substrate, manufacturerscan incorporate pre-made components into electronic devices and systems.Because the semiconductor packages include sophisticated functionality,electronic devices can be manufactured using cheaper components and astreamlined manufacturing process. The resulting devices are less likelyto fail and less expensive to manufacture resulting in a lower cost forconsumers.

FIGS. 2 a-2 c show exemplary semiconductor packages. FIG. 2 aillustrates further detail of DIP 64 mounted on PCB 52. Semiconductordie 74 includes an active region containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within the die and are electricallyinterconnected according to the electrical design of the die. Forexample, the circuit may include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements formedwithin the active region of semiconductor die 74. Contact pads 76 areone or more layers of conductive material, such as aluminum (Al), copper(Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag), and areelectrically connected to the circuit elements formed withinsemiconductor die 74. During assembly of DIP 64, semiconductor die 74 ismounted to an intermediate carrier 78 using a gold-silicon eutecticlayer or adhesive material such as thermal epoxy. The package bodyincludes an insulative packaging material such as polymer or ceramic.Conductor leads 80 and wire bonds 82 provide electrical interconnectbetween semiconductor die 74 and PCB 52. Encapsulant 84 is depositedover the package for environmental protection by preventing moisture andparticles from entering the package and contaminating die 74 or wirebonds 82.

FIG. 2 b illustrates further detail of BCC 62 mounted on PCB 52.Semiconductor die 88 is mounted over carrier 90 using an underfill orepoxy-resin adhesive material 92. Wire bonds 94 provide first levelpacking interconnect between contact pads 96 and 98. Molding compound orencapsulant 100 is deposited over semiconductor die 88 and wire bonds 94to provide physical support and electrical isolation for the device.Contact pads 102 are formed over a surface of PCB 52 using a suitablemetal deposition such electrolytic plating or electroless plating toprevent oxidation. Contact pads 102 are electrically connected to one ormore conductive signal traces 54 in PCB 52. Bumps 104 are formed betweencontact pads 98 of BCC 62 and contact pads 102 of PCB 52.

In FIG. 2 c, semiconductor die 58 is mounted face down to intermediatecarrier 106 with a flip chip style first level packaging. Active region108 of semiconductor die 58 contains analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed according to the electrical design of the die.For example, the circuit may include one or more transistors, diodes,inductors, capacitors, resistors, and other circuit elements withinactive region 108. Semiconductor die 58 is electrically and mechanicallyconnected to carrier 106 through bumps 110.

BGA 60 is electrically and mechanically connected to PCB 52 with a BGAstyle second level packaging using bumps 112. Semiconductor die 58 iselectrically connected to conductive signal traces 54 in PCB 52 throughbumps 110, signal lines 114, and bumps 112. A molding compound orencapsulant 116 is deposited over semiconductor die 58 and carrier 106to provide physical support and electrical isolation for the device. Theflip chip semiconductor device provides a short electrical conductionpath from the active devices on semiconductor die 58 to conductiontracks on PCB 52 in order to reduce signal propagation distance, lowercapacitance, and improve overall circuit performance. In anotherembodiment, the semiconductor die 58 can be mechanically andelectrically connected directly to PCB 52 using flip chip style firstlevel packaging without intermediate carrier 106.

FIGS. 3 a-3 k illustrate a process of forming a semiconductor devicehaving 3D inductors made with a prefabricated pillar frame placed oversemiconductor die and inductor core. In FIG. 3 a, a sacrificial ortemporary reusable substrate or carrier 120 contains base material suchas silicon, polymer, polymer composite, metal, ceramic, glass, glassepoxy, beryllium oxide, tape, or other suitable low-cost, rigid materialfor structural support.

Semiconductor die or components 122 are mounted to carrier 120 withcontact pads 124 oriented downward over the carrier. Semiconductor die122 each include an active region 126 containing analog or digitalcircuits implemented as active devices, passive devices, conductivelayers, and dielectric layers formed within the die and electricallyinterconnected according to the electrical design and function of thedie. For example, the circuit may include one or more transistors,diodes, and other circuit elements formed within active surface 126 toimplement baseband analog circuits or digital circuits, such as digitalsignal processor (DSP), ASIC, memory, or other signal processingcircuit. Semiconductor die 122 may also contain IPD, such as inductors,capacitors, and resistors, for RF signal processing. Semiconductor die122 can be a flipchip type device or wire bond type device. In anotherembodiment, a discrete component can be mounted over carrier 120.

A preformed inductor core 128 is mounted over carrier 120 betweensemiconductor die 122. The inductor core 128 is typically surfacemounted at designated locations on carrier 120. Alternatively, inductorcore 128 can be deposited by PVD, CVD, or other suitable depositionprocess. The inductor core 128 can be suitable either crystalline ornon-crystalline ferromagnetic material or ferromagnetic compositematerial. In other embodiment, inductor core 128 can include alloys suchas FeOFe2O3, NiOFe2O3, CuOFe2O3, or MgOFe2O3.

A prefabricated pillar frame 130 is mounted over semiconductor die 122and inductor core 128, as shown in FIGS. 3 c-3 d. In one embodiment,prefabricated pillar frame 130 is made with Cu using leadframetechnology. Pillar frame 130 includes a flat plate 132 with a pluralityof bodies 134 a-134 f integrated with plate 132 and separated bycavities 136. Bodies 134 a-134 f are sufficiently thick to extend downto carrier 120 when pillar frame 130 is mounted over semiconductor die122. An optional adhesive or thermal interface material 138 provides asecure physical contact between plate 132 and a back surface ofsemiconductor die 122. A plurality of openings 140 is formed throughplate 132 into cavities 136. The prefabricated pillar frame 130 issimple to manufacture and cost effective in comparison to the plated TMVpillars discussed in the background.

FIG. 3 d shows pillar frame 130 mounted over semiconductor die 122.Bodies 134 a and 134 d are vertical (z-direction) interconnect pillars.The inductor core 128 is disposed in cavity 136 between bodies 134 b-134c and between bodies 134 e-134 f. Bodies 134 b, 134 c, 134 e, and 134 fare inductor pillars around inductor core 128.

FIG. 3 e shows an encapsulant or molding compound 146 deposited oversemiconductor die 122 and prefabricated pillar frame 130 using a pasteprinting, compressive molding, transfer molding, liquid encapsulantmolding, vacuum lamination, or other suitable applicator. Theencapsulation process disperses encapsulant 146 through openings 140into cavities 136 below pillar frame 130. Encapsulant 146 can be polymercomposite material, such as epoxy resin with filler, epoxy acrylate withfiller, or polymer with proper filler. Encapsulant 146 is non-conductiveand environmentally protects the semiconductor device from externalelements and contaminants. Encapsulant 146 encloses semiconductor die122, inductor core 128, and bodies 134 a-34 f.

In FIG. 3 f, grinder 148 removes a portion of pillar frame 130,including plate 132 and adhesive layer 138, to planarize the surface andexpose encapsulant 146 in cavities 136. The remaining portion of pillarframe 130 between semiconductor die 122 becomes conductive pillars orposts 134 a and 134 d for vertical z-direction interconnection, andinductor pillars 134 b, 134 c, 134 e, and 134 f for RF signalprocessing. Alternatively, the grinding can be done after removing thesacrificial substrate or temporary carrier 120. FIG. 3 g shows a topview of interconnect pillars 134 a around semiconductor die 122 andinductor pillars 134 b-134 c around inductor core 128, all enclosed inencapsulant 146.

In FIG. 3 h, a build-up interconnect structure 149 is formed over theback surface of semiconductor die 122, encapsulant 146, interconnectpillars 134 a and 134 d, and inductor pillars 134 b-134 c and 134 e-134f. The build-up interconnect structure 149 includes at least oneinsulating or passivation layer. For example, passivation layer 150 isformed with PVD, CVD, printing, sintering, or thermal oxidation. Thepassivation layer 150 can be dielectric polymer insulation materials,such as low temperature cured photosensitive resist. Alternatively,passivation layer 150 can be one or more layers of silicon dioxide(SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalumpentoxide (Ta2O5), aluminum oxide (Al2O3), or other material havingsimilar insulating and structural properties. A portion of passivationlayer 150 is removed by an etching process to expose interconnectpillars 134 a and 134 d, and inductor pillars 134 b-134 c and 134 e-134f.

The build-up interconnect structure 149 further includes at least oneelectrically conductive layer 152 formed over or between passivationlayers, for example, over passivation layer 150. Conductive interconnectpillars 134 a and 134 d, and inductor pillars 134 b-134 c and 134 e-134f using patterning with PVD, CVD, sputtering, electrolytic plating,electroless plating process, or other suitable metal deposition process.Conductive layer 152 can be one or more layers of Al, Cu, Sn, Ni, Au,Ag, or other suitable electrically conductive material. Conductive layer152 is electrically connected to interconnect pillars 134 a and 134 d toprovide vertical, z-direction interconnect. Conductive layer 152 is alsoelectrically connected between rows of inductor pillars 134 b-134 c and134 e-134 f, as shown in FIG. 3 j, to provide an integrated 3D inductorcoiled around inductor core 128.

In FIG. 3 i, carrier 120 is removed by chemical etching, mechanicalpeel-off, CMP, mechanical grinding, thermal bake, laser scanning, or wetstripping. A build-up interconnect structure 153 is formed over thefront surface of semiconductor die 122, encapsulant 146, interconnectpillars 134 a and 134 d, and inductor pillars 134 b-134 c and 134 e-134f. The build-up interconnect structure 153 includes at least oneinsulating or passivation layer 154 formed with PVD, CVD, printing,sintering, or thermal oxidation. The passivation layer 154 can bedielectric polymer insulation materials, such as low temperature curedphotosensitive resist. Alternatively, passivation layer 154 can be oneor more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materialhaving similar insulating and structural properties. A portion ofpassivation layer 154 is removed by an etching process to exposeinterconnect pillars 134 a and 134 d, and inductor pillars 134 b-134 cand 134 e-134 f.

The build-up interconnect structure 153 further includes at least oneelectrically conductive layer 156 formed over or between passivationlayers, for example over passivation layer 154, interconnect pillars 134a and 134 d, and inductor pillars 134 b-134 c and 134 e-134 f usingpatterning with PVD, CVD, sputtering, electrolytic plating, electrolessplating process, or other suitable metal deposition process. Conductivelayer 156 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or othersuitable electrically conductive material. Conductive layer 156 iselectrically connected to interconnect pillars 134 a and 134 d toprovide vertical, z-direction interconnect. Conductive layer 156 is alsoelectrically connected between rows of inductor pillars 134 b-134 c and134 e-134 f, as shown in FIG. 3 j, to provide an integrated 3D inductorcoiled around inductor core 128. Conductive layer 156 is electricallyconnected to contact pads 124.

In FIG. 3 k, semiconductor die or components 158 are mounted overbuild-up interconnect structure 149. Solder bumps 160 are electricallyconnected to conductive layer 152. An optional underfill material 162 isdeposited between semiconductor die 158 and conductive layer 152.Semiconductor die 158 each include a substrate and active regioncontaining analog or digital circuits implemented as active devices,passive devices, conductive layers, and dielectric layers formed withinthe die and electrically interconnected according to the electricaldesign and function of the die. For example, the circuit may include oneor more transistors, diodes, and other circuit elements formed withinits active surface to implement baseband analog circuits or digitalcircuits, such as DSP, ASIC, memory, or other signal processing circuit.Semiconductor die 158 may also contain IPD, such as inductors,capacitors, and resistors, for RF signal processing. Semiconductor die158 can be a flipchip type device or wire bond type device. In anotherembodiment, a discrete semiconductor component can be mounted oversemiconductor die 122. The discrete semiconductor component can be aresistor, capacitor, inductor, or active semiconductor device.

An electrically conductive material is deposited over conductive layer156 using an evaporation, electrolytic plating, electroless plating,ball drop, or screen printing process. The conductive material can beAl, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, withan optional flux material. For example, the conductive material can beeutectic Sn/Pb, high-lead solder, or lead-free solder. The conductivematerial is bonded to conductive layer 156 using a suitable attachmentor bonding process. In one embodiment, the conductive material isreflowed by heating the material above its melting point to formspherical balls or bumps 166. In some applications, bumps 166 arereflowed a second time to improve electrical contact to conductive layer156. The bumps can also be compression bonded to conductive layer 156.Bumps 166 represent one type of interconnect structure that can beformed over conductive layer 156. The interconnect structure can alsouse bond wires, conductive paste, stud bump, micro bump, or otherelectrical interconnect.

The structure is singulated with saw blade or laser cutting tool 164into individual semiconductor devices 168. The IPDs in semiconductordevice 168, including the 3D inductor, provide the electricalcharacteristics needed for high frequency applications, such asresonators, high-pass filters, low-pass filters, band-pass filters,symmetric Hi-Q resonant transformers, matching networks, and tuningcapacitors. The IPDs can be used as front-end wireless RF components,which can be positioned between the antenna and transceiver. Theinductor can be a hi-Q balun, transformer, or coil, operating up to 100Gigahertz. In some applications, multiple baluns are formed on a samesubstrate, allowing multi-band operation. For example, two or morebaluns are used in a quad-band for mobile phones or other global systemfor mobile (GSM) communications, each balun dedicated for a frequencyband of operation of the quad-band device. A typical RF system requiresmultiple IPDs and other high frequency circuits in one or moresemiconductor packages to perform the necessary electrical functions.

FIG. 4 shows an embodiment of the semiconductor device having the 3Dinductor made with the prefabricated pillar frame, without theinterconnect pillars. The inductor pillars 170 a and 170 b are formedaround inductor core 172, using a process similar to FIGS. 3 a-3 k. Thebuild-up interconnect layer 149 can be optional if passivation layer 150is part of the encapsulation and conductive layer 152 is fabricated inlead frame technology by half etching other portions of the frame.

FIG. 5 shows an embodiment of the semiconductor device with multiple 3Dinductors made with the prefabricated pillar frame. The inductor pillars180 a and 180 b are formed around inductor core 182, and inductorpillars 180 c and 180 d are formed around inductor core 184, using aprocess similar to FIGS. 3 a-3 k. The build-up interconnect layer 149can be optional if passivation 150 is part of the encapsulation andconductive layer 152 is fabricated in lead frame technology by halfetching other portions of the frame.

FIG. 6 shows an embodiment of the semiconductor device having stackedsemiconductor die and multiple 3D inductors made with the prefabricatedpillar frame. A back surface of semiconductor die 190 is mounted to aback surface of semiconductor die 192 with an adhesive 193. Contact pads194 of semiconductor die 190 are oriented upward and electricallyconnect to conductive layer 152 of build-up interconnect structure 149.Contact pads 196 of semiconductor die 192 are oriented downward andelectrically connect to conductive layer 156 of build-up interconnectstructure 153. The inductor pillars 198 a and 198 b are formed aroundinductor core 200, and inductor pillars 198 c and 198 d are formedaround inductor core 202, using a process similar to FIGS. 3 a-3 k.

FIG. 7 shows an embodiment of the semiconductor device havingside-by-side semiconductor die 206 and multiple 3D inductors made withthe prefabricated pillar frame. Contact pads 208 of semiconductor die206 are oriented downward and electrically connect to conductive layer156 of build-up interconnect structure 153. The inductor pillars 210 aand 210 b are formed around inductor core 212, and inductor pillars 210c and 210 d are formed around inductor core 214, using a process similarto FIGS. 3 a-3 k.

FIG. 8 shows an embodiment of the semiconductor device with the 3Dinductor made with the prefabricated pillar frame and a shielding layer220 formed over semiconductor die 122 to reduce inter-deviceinterference of the IPD. Shielding layer 220 can be Cu, Al, ferrite orcarbonyl iron, stainless steel, nickel silver, low-carbon steel,silicon-iron steel, foil, epoxy, conductive resin, and other metals andcomposites capable of blocking or absorbing EMI, RFI, and otherinter-device interference. Shielding layer 220 can also be a non-metalmaterial such as carbon-black or aluminum flake to reduce the effects ofEMI and RFI. Shielding layer 220 thermally contacts the backside ofsemiconductor die 122. Shielding layer 220 is electrically connected toa low-impedance ground point through conductive layer 152, interconnectpillars 134 a, and solder bump 166. Shielding layer 220 also dissipatesheat generated by semiconductor die 122.

In FIG. 9, the semiconductor device with the 3D inductor made with theprefabricated pillar frame further includes a thin film capacitor 222 isformed in build-up interconnect layer 149, and thin film capacitor 224is formed in build-up interconnect layer 153. In addition, a thin filmresistor 226 is formed in build-up interconnect layer 149, and thin filmresistor 228 is formed in build-up interconnect layer 153. The thin filmcapacitors 222-224 and thin film resistor 226-228 constitute additionalIPDs that can be formed in build-up interconnect structures 149 and 153.

In FIG. 10, the semiconductor device with 3D inductor made with theprefabricated pillar frame further includes discrete semiconductorcomponents 230 and 232 are formed over build-up interconnect layer 149and electrically connected to conductive layer 152.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A method of making a semiconductor device, comprising: providing acarrier; mounting a semiconductor component over the carrier; forming aninductor core over the carrier; mounting a pillar frame over the carrierand semiconductor component, the pillar frame including a plurality ofbodies with a first portion of the bodies being disposed around theinductor core; depositing an encapsulant around the semiconductorcomponent, plurality of bodies, and inductor core; removing a portion ofthe pillar frame while leaving the first portion of the bodies to forminductor pillars; forming a first interconnect structure over a firstsurface of the encapsulant; removing the carrier; and forming a secondinterconnect structure over a second surface of the encapsulant oppositethe first interconnect structure, the first and second interconnectstructures being electrically connected to the inductor pillars to forma 3D inductor.
 2. The method of claim 1, wherein the inductor coreincludes ferromagnetic material.
 3. The method of claim 1, whereinremoving the portion of the pillar frame further leaves a second portionof the bodies to form an interconnect pillar.
 4. The method of claim 3,further including stacking a plurality of the semiconductor componentselectrically connected through the interconnect pillar.
 5. The method ofclaim 3, further including disposing a plurality of the semiconductorcomponents side-by-side electrically connected through the interconnectpillar.
 6. The method of claim 1, further including forming a shieldinglayer over the semiconductor component.
 7. The method of claim 1,further including forming an integrated passive device within the firstor second interconnect structures.
 8. A method of making a semiconductordevice, comprising: providing a carrier; mounting a semiconductorcomponent over the carrier; mounting a pillar frame over the carrier andsemiconductor component; depositing an encapsulant over thesemiconductor component and pillar frame; removing a portion of thepillar frame, wherein a first remaining portion of the pillar frameprovides inductor pillars; forming a first interconnect structure over afirst surface of the encapsulant; removing the carrier; and forming asecond interconnect structure over a second surface of the encapsulantopposite the first interconnect structure, the first and secondinterconnect structures being electrically connected to the inductorpillars to form a 3D inductor.
 9. The method of claim 8, wherein asecond remaining portion of the pillar frame provides an interconnectpillar.
 10. The method of claim 8, wherein the first or secondinterconnect structure is electrically connected to a contact pad of thesemiconductor component.
 11. The method of claim 8, further includingforming a shielding layer over the semiconductor component.
 12. Themethod of claim 8, further including forming an integrated passivedevice within the first or second interconnect structures.
 13. Themethod of claim 8, further including forming a discrete semiconductorcomponent over the first interconnect structure.
 14. A method of makinga semiconductor device, comprising: providing a carrier; mounting asemiconductor component over the carrier; mounting a pillar frame overthe carrier and semiconductor component; depositing an encapsulant overthe semiconductor component and pillar frame; removing a portion of thepillar frame, wherein a first remaining portion of the pillar frameprovides inductor pillars; and forming a first interconnect structureover a first surface of the encapsulant, the first interconnectstructure being electrically connected to the inductor pillars to form a3D inductor.
 15. The method of claim 14, further including: removing thecarrier; and forming a second interconnect structure over a secondsurface of the encapsulant opposite the first interconnect structure,the first and second interconnect structures being electricallyconnected to the inductor pillars to form the 3D inductor.
 16. Themethod of claim 15, further including forming an integrated passivedevice within the first or second interconnect structures.
 17. Themethod of claim 14, further including forming an inductor core over thecarrier, the inductor pillars being disposed around the inductor core.18. The method of claim 14, wherein a second remaining portion of thepillar frame provides an interconnect pillar.
 19. The method of claim14, further including forming a shielding layer over the semiconductorcomponent.
 20. The method of claim 14, further including forming aplurality of 3D inductors with the inductor pillars.
 21. A semiconductordevice, comprising: a semiconductor component; an inductor core disposedin proximity to the semiconductor component; a pillar frame mounted overthe semiconductor component and inductor core; an encapsulant depositedover the semiconductor component, pillar frame, and inductor core,wherein a portion of the pillar frame is removed to form inductorpillars around the inductor core; a first interconnect structure formedover a first surface of the encapsulant; and a second interconnectstructure formed over a second surface of the encapsulant opposite thefirst interconnect structure, the first and second interconnectstructures being electrically connected to the inductor pillars to forma 3D inductor.
 22. The semiconductor device of claim 21, whereinremoving the portion of the pillar frame leaves an interconnect pillar.23. The semiconductor device of claim 21, further including a shieldinglayer formed over the semiconductor component.
 24. The semiconductordevice of claim 21, further including an integrated passive deviceformed within the first or second interconnect structures.
 25. Thesemiconductor device of claim 21, further including a plurality of 3Dinductors formed with the inductor pillars.